Discuss Help Regarding JK Flip Flop Question in the Electrical Forum area at ElectriciansForums.net

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KennyKen

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Hi Guys, Undertaking a PLC Course and cant seem to get my head around the pulse diagram. Which activates Q and Qbar on the Negative trailing edge. Pointers in the right direction fully appreciated

i'll show you my attempt which was wrong...

The Question is - Complete the timing diagram for a clocked JK Flip flop. Add the output status of Q and ¯Q for the clock pulses on the negative or trailing edge transition

Truth Table 0 - 0 No change
J - 1 = Q - 1
K - 1 = QBar - 1
J - 1 + K - 1 = Toggle
 

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We're talking about a negative-edge-triggered JK here, it seems (positive exist as well).
Before the first neg edge, you don't know the output state so you would have to omit it or show it as don't care. Then at the neg edge of each clock cycle:

1. J=1, K=0, output set to Q.
2. J=1, K=0, output set again to Q i.e. does not change
3. J=K=0, no change.
4. J=K=0, no change.
5. J=1, K=0, output set again to Q i.e. does not change.
6. J=1, K=0, output set again to Q i.e. does not change.
7. J=K=1, output toggles to /Q
8. J=K=0, no change.

So there's only one transition, at cycle 7, when the flop toggles.
Note how there are two situations that cause no change; J=K=0 when the flop does nothing, and J=J', K=K' when the same state is re-asserted. Likewise there are two situations that cause an output transition, J=K=1 which toggles the flop, and J=/J', K=/K' which asserts the complement of the previous state.
 
Last edited:
We're talking about a negative-edge-triggered JK here, it seems (positive exist as well).
Before the first neg edge, you don't know the output state so you would have to omit it or show it as don't care. Then at the neg edge of each clock cycle:

1. J=1, K=0, output set to Q.
2. J=1, K=0, output set again to Q i.e. does not change
4. J=K=0, no change.
5. J=1, K=0, output set again to Q i.e. does not change.
6. J=1, K=0, output set again to Q i.e. does not change.
7. J=K=1, output toggles to /Q
8. J=K=0, no change.

So there's only one transition, at cycle 7, when the flop toggles.
Note how there are two situations that cause no change; J=K=0 when the flop does nothing, and J=J', K=K' when the same state is re-asserted.

Thanks Mate.... Fully Appreciated
 

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