About Positive Edge Triggered FF J-K Flip-Flop

[_q12x_]

• I am thinking on buying a couple of Positive Edge Triggered J-K FF Flip-Flop.
• Who do you recommend? Who is the Best?
• Or, what did you used so far and from your experience is good enough or super good to use?

Mister @marconi ? or anyone else?
Thank you.
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Heh, nevermind - I buy already this 74LS76
---also, is impossible to delete this thread; hahahahahaha

 

[marconi]

I believe I made a mistake.
I believe I also bought a Negative Edge Triggered IC. Aaaaah. And now I see it.
SN74LS76AN
View attachment 102330
View attachment 102329
When they say 'LS76A I believe they refer to this sector SN74LS76AN from the name. Correct?
Im so screwed.

Item numbers for a device really do matter - a good learning point for you. Generally the later numbers and letters of an item number refer to derivative, options or performance for the main device.

 

[_q12x_]

I managed to make it work ! Specifically for 7473 FF ! Read the note for C1 in the bottom of the image.

 

[_q12x_]

I made multiple tests.
Also with your circuit and it does not work.
I also put the osciloscope. It can read the 500ms from the button debounce circuit just fine. But absolutely nothing on the FF clock pin. I tried a lot of time sequence, from 1s to its minimum of 10us. Nothing. I believe this signal MAY be too fast even for my osciloscope to catch it. Thats interesting !!! And I have top of the game osciloscope. Oau.
And I am speacking from the point of view of both FF's. The one that is working with the 7473 and the one that is not working with a 4027.

 

[marconi]

The is a subtle difference between the 7473 and the 7476/4027/7493 flip flops. Whereas 76, 27 and 93 are edge triggered the 73 is level triggered. In my attached electrical art the clock pulse edges are marked 4(leading/positive) and 3(trailing/negative) and the levels are marked in green as 1(Logic 1) or 2(Logic 0).

Briefly, the trigger to change the FF's state is based on detecting when the clock is at either logic 1 or logic 0 for the level triggered FF 7473. The others are triggered when they detect the clock waveform is changing from 0 to 1 ie rising or falling ie 1 to 0.

The 73 uses the logic 1 level. The 76/27/93 use the leading edge; the 76A/27A/93A* use the trailing edge.

I think your C1 is working by being quickly charged by the 1kR - during the brief interval when Qn changes from 111 to 000 - to extend the period of time the Reset signal R is at Logic level 1 so that it is long enough for the 7473 to detect it as such and thence toggle the FF. On becoming 111 the R goes to logic 1 but does not instantaneously drop now to logic 0 at 000 - R has been stretched a tiny bit in time. The 73 data sheet says the minimum time for the clock to be at logic 1 is 20nanoSeconds.

* I am pretty sure there is a 93A which uses the trailing edge but I don't have time right now to confirm that.

 

[pirate]

Just thought I would mention that I am completely out of my depth here! Great to see a discussion between folk who have a completely different knowledge-base from me.
I can, however, make a really nice paella!
Seriously, it's amazing to see stuff that's so different from the norm, and I love this forum for the variety it affords.

 

[marconi]

The 73 data sheet says the minimum time for the clock to be at the level for logic 1 is 20nanoSeconds. Your RC circuit has a time constant T of about 10exp3 x 50 x 10 exp(-12) = 50 x 10exp(-9) or 50 nanoSecond so greater than 20nS which is good.

 

[_q12x_]

Luck is one of my daily tool and I am counting on it when doing a lot of different permutations in my circuit to make it blody work. Haha. Someone actually measured the clock impulse and he got 50ns but for other cct using other FF. Not specifically for mine and not for my circuit per say. It was standard circuit as we did until this odd one here.
"I also put my DSO138 osciloscope !!!!. It can read the 500ms from the button debounce circuit just fine. But absolutely nothing on the FF clock pin. I tried a lot of time sequence, from 1s to its minimum of 10us. Nothing. I believe this signal MAY be too fast even for my osciloscope to catch it." And my other friend from the other side, confirm it with it's 50ns on his osciloscope. But again on normal cct, not mine. So my hercules DSO138 is as bad as I know it. The 50ns is way under its minimum limit.
Thanks for trying mister @marconi and also thanks to the gallery here, haha.

 

[_q12x_]

I was wondering what may be the difference between 7473 and the other 2 blackSheep that didnt worked: 7476 and 4027. In terms of clock speed reading. 7473 clock input is a bit lazy compared to the other 2? Thats the only conclusion I can draw, empirically of course. In other words, the blackSheeps are having way more faster input clock response and sensitivity to the signal than the more lazy 7473.

 

[marconi]

Good morning from sunny London. I am drinking a coffee called 'Shanghai' by Nespresso for the first time - delicious.

I looked up the maximum clock rate and minimum clock pulse duration for the FFs (read frequency typical and maximum and minimum clock pulse duration at Logic 1):

7473 15MHz typ 20MHz max 20nS

7493 32MHz 42MHz 15nS

7476 15MHz 25MHz 20nS

4027:
3.5MHz 140nS at 5V Vcc
8 MHz 60nS at 10V Vcc
12MHz 40nS at 15 Vcc

You can see the slow performance of the 4027 operating at 5V Vcc which is still slower than the other three when Vcc is 15V. This tends to indicate a couple of reasons it struggles to respond to the fast reset pulse R.

 

[pc1966]

Using diode (or any simple logic) like that to reset on a specific pattern is likely to give rise to this sort of timing issues. You typically have two options here to properly fix is:

• Add a pair of inverters of the slowest logic family (4069 or similar if using 4000B series flip-flops) between the decoding (i.e. R4 / C1 / diodes joints) and output of the series pair of inverters to the reset pin. Basically you get a reset pulse that is at least two gate-delays long and so should be able to clock a flip-flop from the same family.
• Decode the second-last state (essentially the last "permanent" state) using logic and then use a synchronous reset/preset so on the next clock edge it goes back to the desired start state (e.g. 0 or any other pattern). In this case the reset pulse is exactly one clock cycle long and so if your clock rate matches all of the logic family's speed limits it works.

If you want to design reliable logic then synchronous operation is by far the easiest route to go!