Yield Loss from low minimum dc input voltage

[T0M0]

Hi All - last post today.

Can someone explain yield loss to me?

Run a config through sunny design which suggests yield loss. It is suggesting the min volt will not be acheived for the extremety of the cell temp range.
When I do standard Voc of array, it exceeds min dc input voltage and start up voltage.

In other words,
min inverter input voltage and start up voltage = 300V
Voc = 315V (STC)
If the more normal PV voltage = 270V (say), what effect does this have on performance and start up volt? Is this what sunny design suggests as yield loses?

Hope this makes sense as I found this difficult to articulate.

Thanks for reading - T0M0

 

[lamb]

Voc is only relevant for the maximum permitted inverter voltage. Vmpp is the relevant figure for minimum input voltage.